Verification Engineer - IP Infrastructure & Methodology - #442358

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The Role

We are the Multimedia & Graphics Infrastructure / Methodology team based in Markham, Ontario, Canada. We are currently seeking an Verification Engineer - IP Infrastructure & Methodology who will focus on driving modeling and verification frameworks, methodology and related infrastructure, and cutting-edge HW acceleration. As a member of this progressive team, you will be responsible for shaping the future of our design and verification processes, architecting, and implementing verification and modeling frameworks, and deploying seamless design acceleration solutions. You will have direct hands-on exposure to verification methodology, design/debug, flow automation, and framework deployment.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Good interpersonal skills (verbal and written). An organized, enthusiastic self-starter, strong interest in hardware verification methodologies. A person who can really think outside the box!

Key Responsibilities

• Architect, develop and deploy, IP methodology infrastructure used in design & verification.
• Enable re-use of C/C++ based models for use in architecture, functional and performance verification, and software development.
• Develop and adapt infrastructure and models for hardware design, verification and acceleration solution.
• Design and implement models and testbenches in UVM, SystemC and C/C++.
• Automate and improve verification and efficiency.
  
  
  

Preferred Experience

• Developing and integrating high level C++ IP models into UVM-like simulation environments.
• Experience developing IP verification frameworks and with a good understanding of testbenches, processes and flows.
• Automating workflows in a distributed compute environment
• Exposure to HW acceleration for design verification, architectural prototyping, and virtual platforms for SW enablement.
• Exposure to simulation and acceleration environments.
• Strong in C++, preferably on Linux with exposure to Windows platform.
• Good understanding of the UVM concepts and System Verilog language is an asset.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred
  
  
  

Academic Credentials

• Undergrad degree required. BASC/BSEE/CE, or equivalent degree or above preferred
  
  
  

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.